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9042
12-Bit, 41 MSPS A/D Converter
Memory
FEATURES:
* Total dose hardness: - > 300 krad (Si) SEL > 120 MeV-cm2/mg * 41 MSPS minimum sampling rate * 80 dB Spurious-Free Dynamic Range (SFDR) * Package: - 28 pin RAD-PAK(R) flat pack * 595 mW power dissipation * Single 5 volt power supply * On-chip T/H and reference * Two's complement output format * CMOS compatible output levels
DESCRIPTION:
Maxwell Technologies' 9042 12-Bit analog-to-digital converter features a greater than 300 krad (Si) total dose tolerance. Using Maxwell's radiation-hardened RAD-PAK(R) packaging technology, the 9042 realizes a higher performance, and low power consumption. All necessary functions, including trackand-hold (T/H) and reference are included on chip to provide a complete conversion solution. The 9042 runs off of a single +5V supply and provides CMOS-compatible digital outputs at 41 MSPS. Designed specifically to address the needs of wideband, multichannel receivers, the 9042 maintains 80 dB spurious-free dynamic range (SFDR) over a bandwidth of 20 MHz. Noise performance is also exceptional; typical signal to noise ratio is 68 dB. Maxwell Technologies' patented RAD-PAK(R) packaging technology incorporates radiation shielding in the microcircuit package. It eliminates the need for box shielding while providing the required radiation shielding for a lifetime in an orbit or space mission. This product is available with screening up to Maxwell Technologies self-defined Class K.
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12-Bit, 41 MSPS A/D Converter
TABLE 1. 9042 PIN DESCRIPTION
PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 - 27 28 SYMBOL GND DVCC GND ENCODE ENCODE GND GND AIN VOFFSET VREF GND AVCC GND AVCC NC NC D0 (LSB) D1 - D10 D11 (MSB)1 Ground 5V Power Supply (Digital) Ground Encode Input. Data conversion initiated on rising edge. Complement of ENCODE. Drive differently with ENCODE or bypass to Ground for single-ended clock mode. Ground Ground Analog Input. Voltage Offset Input. Sets mid-point of analog input range. Normally tied to VREF through 50 Ohm resistor. Internal Voltage Reference. Nominally 2.4V; normally tied to VOFFSET through 50 Ohm resistor. Bypass to Ground with 0.01 F capacitor. Ground 5V Power Supply (Analog) Ground 5V Power Supply (Analog) No Connects. No Connects. Digital Output Bit (Least Significant Bit). Digital Output Bits. Digital Output Bit (Most Significant Bit). DESCRIPTION
9042
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1. Output coded as twos compliment
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TABLE 2. 9042 ABSOLUTE MAXIMUM RATINGS1
PARAMETER ELECTRICAL Analog Supply Voltage Digital Supply Voltage Analog Input Voltage Analog Input Current Digital Input Voltage (ENCODE) ENCODE, ENCODE Differential Voltage Digital Output Current Package Weight Thermal Impedance ENVIRONMENTAL Maximum Junction Temperature Operating Temperature Range Storage Temperature Range TJ TA TS -55 -65 150 125 150 -40 5.25 0 AVCC DVCC AIN 0 0 0.5 7 7 4.5 20 AVCC 4 40 2.39 SYMBOL MIN TYPICAL MAX
9042
UNIT V V V mA V V mA Grams C/W C
JC
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C C
1. Absolute maximum ratings are limiting values to be applied individually, and beyond which the serviceability of the circuit may be impaired. Functional operability is not necessarily
implied. Exposure to absolute maximum rating conditions for an extended period of time may affect device reliability.
TABLE 3. DELTA LIMITS
PARAMETER I(AVCC) I(DVCC) ICCTOTAL VARIATION 10% of specified value in Table 4 10% of specified value in Table 4 10% of specified value in Table 4
(AVCC = DVCC = +5V 5%; VREF TIED TO VOFFSET THROUGH 50 ; TA = -55C TO +125C PARAMETER Resolution DC ACCURACY No Missing Codes1 Offset Error Offset Tempco Gain Error Gain Tempco REFERENCE OUT VREF2 -55 to 125C -55 to 125C -55 to 125C -55 to 125C -55 to 125C 25C
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TABLE 4. 9042 DC ELECTRICAL CHARACTERISTICS
SYMBOL CONDITION SUBGROUPS
MIN
TYP 12
MAX
UNIT
1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1 2.3 -6.5 -10
Guaranteed 3 25 0 -50 2.4 2.5 6.5 10 mV ppm/C % FS ppm/C V
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12-Bit, 41 MSPS A/D Converter
(AVCC = DVCC = +5V 5%; VREF TIED TO VOFFSET THROUGH 50 ; TA = -55C TO +125C PARAMETER Analog Input (AIN) Input Voltage Range Input Resistance Input Capacitance ENCODE INPUTS1,3 Logic Compatibility4 Logic "1" Voltage Logic "0" Voltage Logic "1" Current (VINH = 5V) Logic "0" Current (VINL = 0V) Input Capacitance DIGITAL OUTPUTS Logic Compatibility Logic "1" Voltage (IOH = 10 A) Logic "0" Voltage (IOL = 10 A) Output Coding POWER SUPPLY Analog Supply Voltage Analog Supply Current Digital Supply Voltage Digital Supply Current Supply Current (Total) Power Dissipation Power Supply Rejection Differential Non-linearity (ENCODE = 20 MSPS) Integral Non-linearity (ENCODE = 20 MSPS) PSRR DNL INL AVCC I AVCC DVCC I DVCC ICCTOTAL -55 to 125C -55 to 125C -55 to 125C -55 to 125C -55 to 125C -55 to 125C 25C -55 to 125C -55 to 125C -55 to 125C 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1 1, 2, 3 1, 2,3 1, 2, 3 -1.0 -1.5 -20 5.0 -5.0 -119 595 1 5 0.3 0.75 1.0 1.5 20 180 990 20 160 VOH VOL 25C -55 to 125C 25C,125C -55 1 1, 2, 3 1, 2 3 3.5 3.5 -0.80 0.90 Twos Compliment CMOS 4.2 VIH VIL IIH IIL -55 to 125C -55 to 125C -55 to 125C -55 to 125C 25C 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1 2.0 0 450 -400 625 -300 2.5 TTL/ CMOS 5.0 0.8 800 -200 -55 to 125C 25C 1, 2, 3 2, 3 1 200 VREF 0.5 250 7 300 SYMBOL CONDITION SUBGROUPS MIN TYP MAX
9042
UNIT V
TABLE 4. 9042 DC ELECTRICAL CHARACTERISTICS
V V A A pF
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V V
V mA V mA mA mW mV/V mV/V LSB LSB
1. Guaranteed by design. 2. VREF is normally tied to VOFFSET through 50 ohms. If VREF is used to provide dc offset to other circuits, it should first be buffered 3. 4. ENCODE driven by single-ended source; ENCODE bypassed to ground through 0.01 F capacitor. ENCODE may also be driven differently in conjunction with ENCODE.
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TABLE 5. 9042 AC ELECTRICAL CHARACTERISTICS1
SYMBOL SNR 25C -55 to 125C 9.6 MHz 19.5 MHz SINAD3 Analog Input @ -1 dBFS 1.2 MHz 9.6 MHz 19.5 MHz Worst Spur4 Analog Input @ -1 dBFS 1.2 MHz 9.6 MHz 19.5 MHz Small Signal Spurios Free Dynamic Range (w/ Dither)5 Analog Input @ 1.2 MHz 9.6 MHz 19.5 MHz Two-Tone IMD Rejection6 F1, F2 @ -7 dBFS Two-Tone SFDR (w/Dither)7 Thermal Noise Analog Input bandwidth8 Transient Response8 Overvoltage Recovery Time8 -55 to 125C -55 to 125C 25C 25C 25C 25C
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9042
(AVCC = DVCC = +5V 5%; ENCODE & ENCODE = 41 MSPS; VREF TIED TO VOFFSET THROUGH 50 ; TA = -55C TO +125C) PARAMETER Signal to Noise Analog Input @ -1 dBFS 1.2 MHz Ratio2 CONDITION SUBGROUPS MIN TYP MAX UNIT dB 4 5, 6 4 5, 6 4 5, 6 ----64 -68 67.5 67.5 67 67 66.5 ------dB 25C -55 to 125C 25C -55 to 125C 25C -55 to 125C 4 5, 6 4 5, 6 4 5, 6 ----64 -67.5 67 67.5 67 67 66.5 ------dBc 25C -55 to 125C 25C -55 to 125C 25C -55 to 125C SFDR 4 5, 6 4 5, 6 4 5, 6 ----73 -80 78 80 78 80 78 ------dBFS
25C -55 to 125C 25C -55 to 125C SINAD
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-55 to 125C
4, 5, 6
----
90 90 90 80 90 0.33 100 10 25
------dBc dBFS LSB rms MHz ns ns
4, 5, 6 4, 5, 6 9 9 9 9
----
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12-Bit, 41 MSPS A/D Converter
TABLE 5. 9042 AC ELECTRICAL CHARACTERISTICS1
SYMBOL CONDITION -55 to 125C -55 to 125C tA Jitter 25C 25C 25C 25C tOD -55 to 125C SUBGROUPS 9, 10, 11 9, 10, 11 9 9 9 9 9, 10, 11 10 10 5 9 14 -250 0.7 MIN 41 5
9042
TYP MAX UNIT MSPS MSPS ps ps rms ns ns ns
(AVCC = DVCC = +5V 5%; ENCODE & ENCODE = 41 MSPS; VREF TIED TO VOFFSET THROUGH 50 ; TA = -55C TO +125C) PARAMETER Maximum Conversion Rate Minimum Conversion Rate8 Aperature Delay Aperature Uncertainty ENCODE Pulse Width High ENCODE Pulse Width Low Output Delay
1. 2. 3. 4. 5. 6. 7. 8.
All AC specifications tested by driving ENCODE and ENCODE differentially. Analog input signal power at -1 dBFS; signal-to-noise ratio (SNR) is the ratio of signal level to total noise (first five harmonics removed). Analog input signal power at -1 dBFS; signal-to-noise and distorsion (SINAD) is the ratio of signal level to total noise + harmonics. Analog input signal power at -1 dBFS; worst spur is the ratio of signal level to worst spur, usually limited by harmonics. Analog input signal power swept from -20 dBFS to -95 dBFS; dither power = -32.5 dBm; dither circuit used on input signal SFDR is ratio of converter full scale to worst spur. Tones at -7dBFS (F1 = 15.3 MHz, F2 = 19.5 MHz); two tone intermodualtion distortion (IMD) rejection is ratio or either tone to worst third order intermod product. Both input tones swept from -20 to -95 dBFS; dither power = -32.5 dBm; dither circuit used on input signal two-tone spurious-free dynamic range (SFDR) is the ratio of converter full scale to worst spur. Guaranteed by design.
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FIGURE 1. TIMING DIAGRAM
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12-Bit, 41 MSPS A/D Converter
FIGURE 2. ANALOG INPUT STAGE EQUIVALENT CIRCUIT
9042
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FIGURE 3. ENCODE INPUTS EQUIVALENT CIRCUIT
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FIGURE 4. COMPENSATION PIN, C1 EQUIVALENT CIRCUIT
9042
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12-Bit, 41 MSPS A/D Converter
9042
FIGURE 5. DIGITAL OUTPUT STAGE EQUIVALENT CIRCUIT
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FIGURE 6. 2.4 V REFERENCE EQUIVALENT CIRCUIT
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FIGURE 7. SINGLE TONE AT 1.2 MHZ
9042
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FIGURE 8. SINGLE TONE AT 9.6 MHZ
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12-Bit, 41 MSPS A/D Converter
FIGURE 9. SINGLE TONE AT 19.5 MHZ
9042
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FIGURE 10. HARMONICS VS. AIN
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12-Bit, 41 MSPS A/D Converter
FIGURE 11. NOISE VS. AIN
9042
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FIGURE 12. HARMONICS VS. AIN
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12-Bit, 41 MSPS A/D Converter
FIGURE 13. TWO TONES AT 15.3 MHZ AND 19.5 MHZ
9042
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FIGURE 14. SINGLE TONE SFDR
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FIGURE 15. TWO TONES SFDR
9042
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FIGURE 16. SNR WORST HARMONIC VS. ENCODE
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12-Bit, 41 MSPS A/D Converter
FIGURE 17. SNR WORST CASE SPURIOUS VS. DUTY CYCLE
9042
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FIGURE 18. NPR OUTPUT SPECTRUM
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THEORY OF OPERATION
9042
The 9042 analog-to-digital converter (ADC) employs a twostage subrange architecture. This design approach ensures 12-bit accuracy, without the need for laser trim, at low power. As shown in the functional block diagram, the 1 V p-p SingleEnded analog input, centered at 2.4 V, drives a single-in to differential-out amplifier, A1. The output of A1 drives the first track-and-hold, TH1. The high state of the ENCODE pulse places TH1 in hold mode. The held value of TH1 is applied to the input of the 6-bit coarse ADC. The digital output of the coarse ADC drives a 6-bit DAC; the DAC is 12 bits accurate. The output of the 6-bit DAC is subtracted from the delayed analog signal at the input to TH3 to generate a residue signal. TH2 is used as an analog pipeline to null out the digital delay of the coarse ADC. The residue signal is passed to TH3 on a subsequent clock cycle where the signal is amplified by the residue amplifier, A2, and converted to a digital word by the 7-bit residue ADC. One bit of overlap is used to accommodate any linearity errors in the coarse ADC. The 6-bit coarse ADC word and 7-bit residue word are added together and corrected in the digital error correction logic to generate the output word. The result is a 12-bit parallel digital word which is CMOS-compatible, coded as twos complement.
APPLYING THE 9042
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Encoding the 9042
The 9042 is designed to interface with TTL and CMOS logic families. The source used to drive the ENCODE pin(s) must be clean and free from jitter. Sources with excessive jitter will limit SNR (ref. Equation 1 under "Noise Floor and SNR"). Figure 19. Single-Ended TTL/CMOS Encode
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12-Bit, 41 MSPS A/D Converter
9042
The 9042 encode inputs are connected to a differential input stage (See Figure 3). With no input connected to either the ENCODE or input, the voltage dividers bias the inputs to 1.6 volts. For TTL or CMOS usage, the encode source should be connected to ENCODE. ENCODE should be decoupled using a low inductance or microwave chip capacitor to ground. Devices such as AVX 05085C103MA15, a 0.01 mF capacitor, work well. If a logic threshold other than the nominal 1.6 V is required, the following equations show how to use an external resistor, RX, to raise or lower the trip point (See Figure 3; R1 = 17k, R2 = 8k).
to lower logic threshold. Figure 20. Lower Logic Threshold for Encode
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to raise logic threshold.
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Figure 21. Raise Logic Threshold for Encode
9042
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While the single-ended encode will work well for many applications, driving the encode differentially will provide increased performance. Depending on circuit layout and system noise, a 1 dB to 3 dB improvement in SNR can be realized. It is not recommended that differential TTL logic be used however, because most TTL families that support complementary outputs are not delay or slew rate matched. Instead, it is recommended that the encode signal be accoupled into the ENCODE and ENCODE pins. The simplest option is shown below. The low jitter TTL signal is coupled with a limiting resistor, typically 100 ohms, to the primary side of an RF transformer (these transformers are inexpensive and readily available; part# in Figure 22 is from Mini-Circuits). The secondary side is connected to the ENCODE and ENCODE pins of the converter. Since both encode inputs are self biased, no additional components are required. Figure 22. TTL Source - Differential Encode
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12-Bit, 41 MSPS A/D Converter
9042
If no TTL source is available, a clean sine wave may be substituted. In the case of the sine source, the matching network is shown below. Since the matching transformer specified is a 1:1 impedance ratio, R, the load resistor should be selected to match the source impedance. The input impedance of the 9042 is negligible in most cases. Figure 23. Sine Source - Differential Encode
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If a low jitter ECL clock is available, another option is to accouple a differential ECL signal to the encode input pins as shown below. The capacitors shown here should be chip capacitors but do not need to be of the low inductance variety. Figure 24. Differential ECL for Encode
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12-Bit, 41 MSPS A/D Converter
9042
As a final alternative, the ECL gate may be replaced by an ECL comparator. The input to the comparator could then be a logic signal or a sine signal. Figure 25. ECL Comparator for Encode
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Care should be taken not to overdrive the encode input pin when ac coupled. Although the input circuitry is electrically protected from over or under voltage conditions, improper circuit operations may result from overdriving the encode input pins.
Driving the Analog Input
Because the 9042 operates off of a single +5 V supply, the analog input range is offset from ground by 2.4 volts. The analog input, AIN, is an operational amplifier configured in an inverting mode (ref. Equivalent Circuits: Analog Input Stage). VOFFSET is the noninverting input which is normally tied through a 50 ohm resistor to VREF (ref. Equivalent Circuits: 2.4 V Reference). Since the operational amplifier forces its inputs to the same voltage, the inverting input is also at 2.4 volts. Therefore, the analog input has a Thevenin equivalent of 250 ohms in series with a 2.4 volt source. It is strongly recommended that the 9042's internal voltage reference be used for the amplifier offset; this reference is designed to track internal circuit shifts over temperature.
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Figure 26. Analog Input Offset by +2.4 V Reference
9042
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Although the 9042 may be used in many applications, it was specifically designed for communications systems which must digitize wide signal bandwidths. As such, the analog input was designed to be ac-coupled. Since most communications products do not down-convert to dc, this should not pose a problem. One example of a typical analog input circuit is shown below. In this application, the analog input is coupled with a high quality chip capacitor, the value of which can be chosen to provide a low frequency cutoff that is consistent with the signal being sampled; in most cases, a 0.1 mF chip capacitor will work well. Figure 27. AC-Coupled Analog Input Signal
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12-Bit, 41 MSPS A/D Converter
9042
Another option for ac-coupling is a transformer. The impedance ratio and frequency characteristics of the transformer are determined by examining the characteristics of the input signal source (transformer primary connection), and the 9042 input characteristics (transformer secondary connection). "RT" should be chosen to satisfy termination requirements of thesource, given the transformer turns ratio. A blocking capacitor is required to prevent 9042 dc bias currents from flowing through the transformer. Figure 28. Transformer-Coupled Analog Input Signal
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When calculating the proper termination resistor, note that the external load resistor is in parallel with the 9042 analog input resistance, 250 ohms. The external resistor value can be calculated from the following equation:
where Z is desired impedance. 9042 A dc-coupled input configuration (shown below) is limited by the drive amplifier performance. The 9042's on-chip reference is buffered using the OP279 dual, rail-to-rail operational amplifier. The resulting voltage is combined with the analog source using an AD9631. Pending improvements in drive amplifiers, this dc-coupled approach is limited to ~75 dB-80 dB of dynamic performance depending on which drive amplifier is used. The AD9631 and OP279 run off 5 V. Figure 29. DC-Coupled Analog Input Circuit
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12-Bit, 41 MSPS A/D Converter
9042
Power Supplies
Care should be taken when selecting a power source. Linear supplies are strongly recommended as switching supplies tend to have radiated components that may be "received" by the 9042. Each of the power supply pins should be decoupled as closely to the package as possible using 0.1 mF chip capacitors. The 9042 has separate digital and analog +5 V pins. The analog supplies and the denoted AVCC digital supply pins are denoted DVCC. Although analog and digital supplies may be tied together, best performance is achieved when the supplies are separate. This is because the fast digital output swings can couple switching noise back into the analog supplies. Note that AVCC must be held within 5% of 5 volts, however the DVCC supply may be varied according to output digital logic family (i.e., DVCC should be connected to the supply for the digital circuitry).
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Output Loading
Care must be taken when designing the data receivers for the AD9042. It is recommended that the digital outputs drive a series resistor of 499 ohms followed by a CMOS gate like the 74AC574. To minimize capacitive loading, there should only be one gate on each output pin. The digital outputs of the 9042 have a unique constant slew rate output stage. The output slew rate is about 1 V/ns independent of output loading. A typical CMOS gate combined with PCB trace and through hole will have a load of approximately 10 pF. Therefore as each bit switches, 10 mA
of dynamic current per bit will flow in or out of the device. A full- scale transition can cause up to 120 mA (12bits 10 mA/bit) of current to flow through the digital output stage. The series resistor will minimize the output currents that can flow in the output stage. These switching currents are confined between ground and the DVCC pin. Standard TTL gates should be avoided since they can appreciably add to the dynamic switching currents of the 9042.
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12-Bit, 41 MSPS A/D Converter
9042
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28-PIN RAD-PAK(R) FLAT PACKAGE
SYMBOL MIN A b c D E E1 E2 E3 e L Q S1 N 0.375 0.021 0.000 0.129 0.015 0.004 -0.474 -0.255 0.000 DIMENSION NOM 0.142 0.017 0.005 0.820 0.480 -0.260 0.110 0.050 BSC 0.385 0.025 0.077 28 0.395 0.029 -MAX 0.155 0.022 0.009 0.828 0.486 0.506 ---
Note: All dimensions in inches
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12-Bit, 41 MSPS A/D Converter
Important Notice:
9042
These data sheets are created using the chip manufacturer's published specifications. Maxwell Technologies verifies functionality by testing key parameters either by 100% testing, sample testing or characterization. The specifications presented within these data sheets represent the latest and most accurate information available to date. However, these specifications are subject to change without notice and Maxwell Technologies assumes no responsibility for the use of this information. Maxwell Technologies' products are not authorized for use as critical components in life support devices or systems without express written approval from Maxwell Technologies. Any claim against Maxwell Technologies must be made within 90 days from the date of shipment from Maxwell Technologies. Maxwell Technologies' liability shall be limited to replacement of defective parts.
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12-Bit, 41 MSPS A/D Converter
Product Ordering Options
Model Number 9042 RP F X Feature Option Details
9042
Screening Flow
MCM1 K= Maxwell Self-Defined Class K H= Maxwell Self-Defined Class H I = Industrial (testing @ -55C, +25C, +125C) E = Engineering (testing @ +25C)
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Package
F = Flat Pack
Radiation Feature
RP = RAD-PAK(R) package
Base Product Nomenclature
12-Bit, 41 MSPS A/D Converter
1) Products are manufactured and screened to Maxwell Technologies self-defined Class H and Class K flows.
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